Evaluation of IGBT gate parasitics by means of a PEEC based tool

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dc.contributor.authorMadadi, Aryan
dc.contributor.departmentChalmers tekniska högskola / Institutionen för energi och miljösv
dc.contributor.departmentChalmers University of Technology / Department of Energy and Environmenten
dc.date.accessioned2019-07-03T13:07:29Z
dc.date.available2019-07-03T13:07:29Z
dc.date.issued2013
dc.description.abstractIn this thesis work, as a part of SEMikado project, a modeling platform is developed in BusBar Tool for studying the IGBT StakPak gate prints to be used in HVDC Light and SVC Light applications. Parasitic elements of two IGBT StakPak gate print designs have been extracted and the effects of several parameters including emitter plate, couplings and skin effect have been modeled and analyzed. SPICE models obtained from BusBar Tool simulations have been imported into PSpice and have been put into the desired test circuit in each simulation scenario to evaluate the IGBT positions. A PSpice circuital schematics test circuit has been built for studying the separated gate print which provides a better overview on parasitic elements. Two gate print designs have been compared through several simulation scenarios, regarding their parasitic elements, hence maximum voltage overshoots and time delays.
dc.identifier.urihttps://hdl.handle.net/20.500.12380/173817
dc.language.isoeng
dc.setspec.uppsokLifeEarthScience
dc.subjectElkraftteknik
dc.subjectElectric power engineering
dc.titleEvaluation of IGBT gate parasitics by means of a PEEC based tool
dc.type.degreeExamensarbete för masterexamensv
dc.type.degreeMaster Thesisen
dc.type.uppsokH
local.programmeElectric power engineering (MPEPO), MSc
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