Investigation of high performance configurations on the Evolved Packet Gateway
Typ
Examensarbete för masterexamen
Program
Computer systems and networks (MPCSN), MSc
Publicerad
2020
Författare
Chatziadam, Georgios
Mebrahtu Birhanu, Tsigabu
Modellbyggare
Tidskriftstitel
ISSN
Volymtitel
Utgivare
Sammanfattning
Modern servers today are based on multi-socket motherboards to increase their power
and performance figures. These setups provide CPU interconnection through a high
speed bus. If processes on one CPU need access to memory or devices local to another
CPU, they need to traverse this bus and this adds a delay to the execution time. This
is where the concept of Non-Uniform Memory Access (NUMA) presents as a solution.
Every socket with its local memory is considered a node, that is locked and processes
are not allowed to migrate. This means that loading instructions has low latency, but
they can also access the main memory connected to the other NUMA nodes at a given
penalty cost. The latest CPUs such as the EPYC series from AMD are using this concept
even within the processor module, and there is no possibility to avoid taking into account
NUMA aspects.
There has been a plethora of benchmarks to analyze the impact of NUMA node architecture
on different processors. In this work, we have used the Packet Gateway of the
Evolved Packet Core (EPC) as a test case to investigate the effectiveness of NUMA architecture
on Intel processors on a virtual large-scale distributed production system with
high performance requirements. On the virtualization setups, di erent CPU pining and
deployment strategies are used, while Packet Per Second (pps) is the preferred performance
indicator in systems like the Evolved Packet Gateway (EPG).We further describe
and analyze different scenarios, combining CPU pinning and process placement, within
the virtual machines running the EPG.
Beskrivning
Ämne/nyckelord
NUMA , EPG , Computer Science , Engineering , Project , Thesis