Optimized Pulse Pattern Control Strategy Investigation on Signal Level Hardware in the Loop

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dc.contributor.authorZou, Chenye
dc.contributor.departmentChalmers tekniska högskola / Institutionen för elektrotekniksv
dc.contributor.examinerThiringer, Torbjörn
dc.contributor.supervisorGeorge, Shino
dc.contributor.supervisorIngelström, Pär
dc.date.accessioned2023-09-25T07:23:02Z
dc.date.available2023-09-25T07:23:02Z
dc.date.issued2023
dc.date.submitted2023
dc.description.abstractAbstract Electric vehicles (EVs) are gaining popularity worldwide due to their low cost of use and sustainability. Key components of the EV drivetrain include an inverter and a permanent magnet synchronous machine (PMSM). To better improve their efficiency, optimized pulse pattern (OPP) can be used. However, simulating OPP together with the inverter and motor takes a lot of time because of high computational complexity. This thesis project utilizes a hardware in the loop (HiL) platform to accelerate the simulation. The PMSM and inverter models are running on a fieldprogrammable gate array (FPGA) separately from the controller model to ensure a high sampling rate while the whole system is still running in real time. Then OPP is evaluated with this platform in comparison with the conventional space vector pulse width modulation (SVPWM). The result shows a significant advantage of OPP in reducing inverter switching losses. Finally, the limitation and operating range of the OPP is also discussed in this thesis report.
dc.identifier.urihttp://hdl.handle.net/20.500.12380/307101
dc.language.isoeng
dc.setspec.uppsokTechnology
dc.subjectKeywords: Permanent Magnet Synchronous Machine, Hardware in the Loop, Field- Programmable Gate Array, Space Vector Pulse Width Modulation, Optimized Pulse Pattern.
dc.subjectPermanent Magnet Synchronous Machine
dc.subjectHardware in the Loop
dc.subjectField- Programmable Gate Array
dc.subjectSpace Vector Pulse Width Modulation
dc.subjectOptimized Pulse Pattern
dc.titleOptimized Pulse Pattern Control Strategy Investigation on Signal Level Hardware in the Loop
dc.type.degreeExamensarbete för masterexamensv
dc.type.degreeMaster's Thesisen
dc.type.uppsokH
local.programmeElectric power engineering (MPEPO), MSc
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