VHDL Implementation of Reed-Solomon FEC architecture for high-speed optical communications
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Typ
Examensarbete för masterexamen
Program
Embedded electronic system design (MPEES), MSc
Publicerad
2020
Författare
Shanmugam, Harini
Modellbyggare
Tidskriftstitel
ISSN
Volymtitel
Utgivare
Sammanfattning
In the quest to achieve high data rates, several 100 Gbps Ethernet standards for
backplane, copper cables and fiber optic that include forward error correction based
on Reed–Solomon (RS) codes have been recently approved. This thesis work presents
the design and implementation of a high-throughput Reed-Solomon RS(255, 239)
decoder architecture suitable for those standards. Various error correction decoders
have been formulated through algorithmic transformations of the inversionless
Berlekamp Massey algorithm (IBMA). In this work, a Key Equation Solver
(KES) based on the modified enhanced Parallel Inversionless Berlekamp Massey
algorithm (ePIBMA) is used. Hardware implementation results are presented for
the RS(255, 239) codes over GF(28) that reach 106.03 Gbps when implemented in a
65nm CMOS process. Finally, post synthesis the timing, area and power estimates
generated are also presented.
Beskrivning
Ämne/nyckelord
ASIC , chien search , communications , decoder , error correction , ethernet , fiber optic , forward error correction , galois field , Gbps , hardware , high data rate , high speed , high throughput , IEEE , implementation , key equation solver , Reed- Solomon codes , syndrome calculator , thesis.