VHDL Implementation of Reed-Solomon FEC architecture for high-speed optical communications

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dc.contributor.authorShanmugam, Harini
dc.contributor.departmentChalmers tekniska högskola / Institutionen för data och informationstekniksv
dc.contributor.examinerPeterson, Lena
dc.contributor.supervisorFougstedt, Christoffer
dc.contributor.supervisorLarsson-Edefors, Per
dc.date.accessioned2020-11-02T11:24:33Z
dc.date.available2020-11-02T11:24:33Z
dc.date.issued2020sv
dc.date.submitted2020
dc.description.abstractIn the quest to achieve high data rates, several 100 Gbps Ethernet standards for backplane, copper cables and fiber optic that include forward error correction based on Reed–Solomon (RS) codes have been recently approved. This thesis work presents the design and implementation of a high-throughput Reed-Solomon RS(255, 239) decoder architecture suitable for those standards. Various error correction decoders have been formulated through algorithmic transformations of the inversionless Berlekamp Massey algorithm (IBMA). In this work, a Key Equation Solver (KES) based on the modified enhanced Parallel Inversionless Berlekamp Massey algorithm (ePIBMA) is used. Hardware implementation results are presented for the RS(255, 239) codes over GF(28) that reach 106.03 Gbps when implemented in a 65nm CMOS process. Finally, post synthesis the timing, area and power estimates generated are also presented.sv
dc.identifier.coursecodeMPEESsv
dc.identifier.urihttps://hdl.handle.net/20.500.12380/302018
dc.language.isoengsv
dc.setspec.uppsokTechnology
dc.subjectASICsv
dc.subjectchien searchsv
dc.subjectcommunicationssv
dc.subjectdecodersv
dc.subjecterror correctionsv
dc.subjectethernetsv
dc.subjectfiber opticsv
dc.subjectforward error correctionsv
dc.subjectgalois fieldsv
dc.subjectGbpssv
dc.subjecthardwaresv
dc.subjecthigh data ratesv
dc.subjecthigh speedsv
dc.subjecthigh throughputsv
dc.subjectIEEEsv
dc.subjectimplementationsv
dc.subjectkey equation solversv
dc.subjectReed- Solomon codessv
dc.subjectsyndrome calculatorsv
dc.subjectthesis.sv
dc.titleVHDL Implementation of Reed-Solomon FEC architecture for high-speed optical communicationssv
dc.type.degreeExamensarbete för masterexamensv
dc.type.uppsokH
local.programmeEmbedded electronic system design (MPEES), MSc
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