Implementation of a RISC-V Processor with Hardware Accelerator

Abstract

Due to the approaching end of Moore’s law, there are limits to how fast software can run on processors even in the future. A possible solution is to start doing calculations in hardware instead of software, as this is significantly faster. This project aimed to develop a hardware accelerator for a RISC-V core. This was accomplished by designing a hardware matrix multiplier to run alongside a RISC-V processor. Through testing, it was shown that hardware matrix multiplication is significantly faster than the equivalent computation in software. With this result, the project group was able to implement a method to compute matrices which is much faster than software calculation and can be used for commercial purposes.