Implementation of a RISC-V Processor with Hardware Accelerator
| dc.contributor.author | BLOMKVIST, LUDVIG | |
| dc.contributor.author | OSCARSSON, JONAS IBRAHIMOGLU | |
| dc.contributor.author | NILSSON, LUCAS | |
| dc.contributor.author | STENSEKE, ADAM | |
| dc.contributor.author | WENNERBERG, JOAKIM | |
| dc.contributor.department | Chalmers tekniska högskola / Institutionen för data och informationsteknik | sv |
| dc.contributor.examiner | Pericàs, Miquel | |
| dc.contributor.supervisor | Petersen Moura Trancoso, Pedro | |
| dc.date.accessioned | 2020-10-19T12:56:25Z | |
| dc.date.available | 2020-10-19T12:56:25Z | |
| dc.date.issued | 2019 | sv |
| dc.date.submitted | 2020 | |
| dc.description.abstract | Due to the approaching end of Moore’s law, there are limits to how fast software can run on processors even in the future. A possible solution is to start doing calculations in hardware instead of software, as this is significantly faster. This project aimed to develop a hardware accelerator for a RISC-V core. This was accomplished by designing a hardware matrix multiplier to run alongside a RISC-V processor. Through testing, it was shown that hardware matrix multiplication is significantly faster than the equivalent computation in software. With this result, the project group was able to implement a method to compute matrices which is much faster than software calculation and can be used for commercial purposes. | sv |
| dc.identifier.coursecode | DATX02 | sv |
| dc.identifier.uri | https://hdl.handle.net/20.500.12380/301897 | |
| dc.language.iso | eng | sv |
| dc.setspec.uppsok | Technology | |
| dc.title | Implementation of a RISC-V Processor with Hardware Accelerator | sv |
| dc.type.degree | Examensarbete på kandidatnivå | sv |
| dc.type.uppsok | M2 |