Data- och informationsteknik (CSE) // Computer Science and Engineering (CSE)

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https://odr.chalmers.se/handle/20.500.12380/11

Vi utbildar för framtiden och skapar samhällsnytta genom vår forskning som levandegörs i nära samarbete med näringslivet. Vi bedriver forskning inom computer science, datateknik, software engineering och interaktionsdesign - från grundforskning till direkta tillämpningar. Institutionen har en stark internationell prägel och är delad mellan Chalmers och Göteborgs universitet.

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För forskning och forskningspublikationer, se https://research.chalmers.se/organisation/data-och-informationsteknik/

We are engaged in research and education across the full spectrum of computer science, computer engineering, software engineering, and interaction design, from foundations to applications. We educate for the future, conduct research with high international visibility, and create societal benefits through close cooperation with businesses and industry. The department is joint between Chalmers and the University of Gothenburg.

Studying at the Department of Computer Science and Engineering at Chalmers

For research and research output, please visit https://research.chalmers.se/en/organization/computer-science-and-engineering/

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A Configurable Interface Unit for Telemetry Monitoring in Satellites
(2018) Hagslätt, Fredrik; Johansson, Fredrik; Chalmers tekniska högskola / Institutionen för data- och informationsteknik (Chalmers); Chalmers University of Technology / Department of Computer Science and Engineering (Chalmers)
This report presents a concept for a flexible remote interface unit for telemetry monitoring in satellites. The concept consists of a flexible hardware interface that can be configured by a microcontroller into reading several different types of sensors. An important aspect in the introduced flexibility is the presented method for filtering signals digitally, eliminating the need for slow analog low-pass filters. The feasibility of the concept is verified and its expected performance is evaluated. The performance evaluation is based on acquisition times that are affected by the hardware’s configuration time, the sensor’s settling times and the time needed for digital filtering. The report also summarizes the number and types of sensors on several finished satellites to evaluate how many the proposed concept can cover. Digital filtering together with the evaluation of performance and coverage shows that this concept can be further developed into a flexible design that can cover future projects without the need for major hardware changes, thus reducing development costs.
A Defect-Tolerant Mixed-Grain Reconfigurable Multiprocessor Array
(2014) Khan, Danish Anis; Chalmers tekniska högskola / Institutionen för data- och informationsteknik (Chalmers); Chalmers University of Technology / Department of Computer Science and Engineering (Chalmers)
Defect tolerance at chip level is currently an evolving field. With continues improvement in transistor feature size and device count the reliability of hardware has became a major concern for manufactures and designers alike. Hence a solution that can address defects at lower level while maintaining a small implementation cost could not only help in keeping the manufacturing cost low but also serves as a base for future reliable yet cost effective devices. The topic of this thesis is related to a similar approach for a RISC processor. We began from previously designed coarse grain implementation of a defect tolerant multiprocessor array and supplement it with a fine-grain “wild-card” like block which could replace any one of the defective pipeline stages in the array when required. Thus would improve the availability of the multiprocessor array at high defect rates. However by doing so the performance of implemented pipeline stages suffers from inherit gate delay of the reconfigurable substrate. Therefore the design has been modified to provide functionality at reasonable performance cost. The proposed design offers graceful degradation and in a worst case scenario exhibits a performance & power overhead of 10X and 1.75X respectively as compare to the baseline processor. With respect to area utilization the proposed fine-grain block requires 2.6X the area of single baseline processor, while in terms of availability the benefit of this approach in a 4 core coarse-grain defect tolerant array becomes apparent at defect rates above 1.3 faults per core.
A Fast Radio Burst (FRB) Capture Sys tem for the Onsala Space Observatory
(2021) Jia, Bocheng; Chen, Xiao; Chalmers tekniska högskola / Institutionen för data och informationsteknik; Peterson, Lena; Larsson-Edefors, Per
The discovery of the fast radio burst (FRB) in 2007 was an important moment in astronomy due to FRB’s unique property, which helps astronomers explore how the universe expanded and gives clues to study celestial phenomenons such as the ap pearance of neutron stars. The purpose of this thesis is to explore and develop a new digital backend system for Onsala Space Observatory to capture FRB events in real time and reduce the data rate. A trigger mechanism that can flag the FRB can didates is implemented. Only when potential FRB candidates are detected, signal data would be buffered and saved. We implemented polyphase filterbank channel ization to generate the signal’s spectrum in real time. Moreover, we implemented incoherent de-dispersion algorithms to compensate for the frequency-dependent de lay. Filtering and averaging are introduced to improve an FRB’s signal-to-noise ratio. We first built the system model in MATLAB and analyzed the simulation results. We also demonstrated the hardware implementation of the FRB capturing system and tested the system with a signal generator. The test results showed that our system is able to capture FRB events and reduce the data rate compared to the current system in Onsala Space Observatory.
A Framework for a Relative Real-Time Tracking System Based on Ultra-Wideband Technology
(2017) Ortiz Betancur, Gabriel; Treven, Fredrik; Chalmers tekniska högskola / Institutionen för data- och informationsteknik (Chalmers); Chalmers University of Technology / Department of Computer Science and Engineering (Chalmers)
The growing number of applications in automated robots and vehicles has increased the demand for positioning, locating, and tracking systems. The majority of the current methods are based on machine vision systems and require a direct line of sight (LOS) between the tracking device and the target at all times for carrying out the desired functionalities. This limits the possible applications and makes them vulnerable to disturbances. The method presented in this thesis work aims to remove the continuous LOS requirement and allow for an omnidirectional and accurate tracking method using ultra-wideband (UWB) technology. This is achieved by using a flipped UWB positioning topology where a set of anchors keeps track of the position of a target and maintains a specific distance from it; this is in contrast to regular indoor positioning systems where a target monitors its own position in relation to a set of fixed references. The feasibility of this solution is shown by a tracking device prototype which demonstrates the capabilities of the proposed system and the UWB technology. The results show that the proposed topology is suitable for positioning, tracking and following applications that require a high degree of accuracy at short distances with the possibility of removing the continuous direct LOS requirement.
A Method for Estimation of Safe and Tight WCET in Multicore Memory Hierarchies
(2014) Hashi, Feysal Hadji; Chalmers tekniska högskola / Institutionen för data- och informationsteknik (Chalmers); Chalmers University of Technology / Department of Computer Science and Engineering (Chalmers)
Multicore microprocessors have become the new way to improve the processor performance. Moreover, the multicore processor systems are currently the dominating computer resource in many products like mobile appliances, automotive and space-borne applications. However, the last category’s challenge is that tasks can have various degrees of criticality concerning the response times. Therefore, the aim of this Master’s Thesis is to develop a method to derive a safe (the task execution time can never be longer) and a tight (worst-case execution time is off the real execution time by typically a small factor) worst-case execution time estimates in multicore system with memory hierarchies. The produced method consists of an analytical model and gem5, which is a state-of-the-art computer architecture simulator. This Thesis has surprisingly discovered that the simulated multicore system’s throughput increases by close to linearly with the number of cores. This suggests that, contrary to common belief, it is possible to guarantee a safe worst-case execution time and still enjoy the increase in throughput offered by multicore systems. These findings are therefore encouraging for further investigations. Although, the outcome of this Thesis mainly focuses on LEON4FT, which is a SPARC V8 based System-on-a-Chip, it is also applicable to other multicore systems. Furthermore, the Thesis report introduces the previous studies’ arguments about the transition from uniprocessor to the multicore processors, memory hierarchies as well as worst-case execution time.
A method for predicting hardware resource usage for Electronic Control Units
(2015) Elghoz, Mohammed; Nilsson, Einar; Chalmers tekniska högskola / Institutionen för data- och informationsteknik (Chalmers); Chalmers University of Technology / Department of Computer Science and Engineering (Chalmers)
The telematic gateway unit is used in vehicles for communication with a backoffice. The unit is an Electronic Control Unit (ECU) and the communication could for example be used to send the current position of the vehicle, the status of the vehicle components, or the current up-time of the vehicle to the backoffice. The hardware resources on the telematics gateway unit are limited and with increasing functionality of the unit increasing amounts of hardware resources are needed. This thesis work was carried out on the onboard telematics department of Volvo Group Trucks and the main focus was to find a method to predict the required hardware resources needed when adding or changing functions on the telematics gateway unit. After studying around 60 different articles, 9 interesting approaches were found. Regression analysis was found to be the most suited for predicting the hardware resources. The method that is proposed in the report firstly, gather data regarding the resources used on the telematic gateway unit. Secondly, multiple regression is applied to the gathered data to make the predictions of the hardware resource chosen. Limited tests were carried out on the predicted values, the tests indicated that predictions on the hardware resources were possible. The predictions made with multiple regression can be used to roughly estimate the amount of resources a new function will require. However, implementing the prediction method requires measuring more resource data than is currently done by the onboard telematics department.
A Novel Speculative Pseudo-Parallel Delta-Sigma Modulator Using FPGAs to produce a high-speed digital signal for use in MIMO transmission systems
(2014) Johansson, Jesper; Chalmers tekniska högskola / Institutionen för data- och informationsteknik (Chalmers); Chalmers University of Technology / Department of Computer Science and Engineering (Chalmers)
As digital communication using MIMO antenna technology has emerged as a significant technological breakthrough in modern communications, the need for reconfigurable experimental MIMO systems has increased. This project is a feasibility study of using !⌃ modulators for generating high-speed digital signals on an FPGA chip synchronized to one local oscillator. The targeted performance specifications are a 1 GHz carrier frequency, 100 MHz bandwidth, and 45 dB in-band SNDR. The approach used to achieve the performance specifications is a novel speculative pseudo-parallel !⌃ modulator based on the the method for unrolling a !⌃ modulator proposed by Hatami et al. The speculative modulator structure, although it fails to achieve the tentative system specifications, exhibits a 46 % increase in operating frequency versus the regular Hatami structure. The speculative modulator structure has the potential for further investigation and design space exploration. The main reason for failing to reach the performance goal is suboptimal mapping in the FPGA chip, which leads to relatively long routing delays with 69 % of the delay situated in routing.
A Phase-Locked GaN Oscillator Using a Mechanically Tunable Cavity Resonator
(2022) Oxklint, Alexander; Chalmers tekniska högskola / Institutionen för data och informationsteknik; Chalmers University of Technology / Department of Computer Science and Engineering; Larsson-Edefors, Per; Kuylenstierna, Dan
The demand for wireless data transfer is growing rapidly, and local oscillator phase noise has been identified as a performance limiting factor in radio communication systems. Two ways to reduce phase noise are to use a high power amplifier- and a high quality factor (Q) resonator in the oscillator design, such as a gallium nitride high electron mobility transistor (GaN HEMT) amplifier and a metallic cavity resonator. A free-running cavity oscillator is however a poor choice for use as a local oscillator, since they exhibit poor thermal frequency stability. This thesis presents the design and characterization of a phase-locked GaN HEMT cavity oscillator, utilizing mechanical tuning of the cavity as well as electronic tuning using a varactor. The prototype oscillator works, but performed worse than expected with a phase noise of −103.7 dB at 100 kHz offset, measured at the best operating point. The oscillation frequency of the oscillator was tunable from 11.51 GHz to 12.29 GHz. Furthermore, the phase locked loop (PLL) was not able to lock the phase of the oscillator to a reference due to stability issues. Theoretical evidence that low phase noise can be achieved using this method is however presented, and reasons for the poor performance of the prototype are discussed.
A sensor fusion filter structure based on RBFNN aided Kalman filter in target positioning
(2020) XU, MING; HAN, WENQIAN; Chalmers tekniska högskola / Institutionen för data och informationsteknik; Larsson-Edefors, Per; Peterson, Lena
Nowadays multiple sensors are mounted in one vehicle to obtain reliable data useful for environment perception, Kalman-filter-based multisensor data fusion is commonly adopted in vehicles for target positioning to provide active safety features to the end user. Kalman filter is the optimal solution to numerous data prediction problems as long as the noise is Gaussian. However, non-Gaussian noise or un-modeled noise contained in filter signals can seriously degrade the filter performance. Without a priori knowledge of noise in the system, tuning the parameters of Kalman filter can be difficult. To improve the accuracy of filter estimates, a sensor fusion system that integrates a Kalman filter with a radial basis function neural network (RBFNN) is presented in the thesis. Both extended Kalman filter (EKF) and converted measurement Kalman filter (CMKF) are implemented to verify the univesality of the system. RBFNN is chosen due to its universal function approximation, simple structure and faster learning speed. An incremental constructive method is adopted to design the RBFNN in the project. Filter status (time interval between measurements and estimation results) as well as host information (steering angle and acceleration) are sent as input of RBFNN. The training target is the difference between the conventional filter output and the ground truth from the DAQ system. After training, the neural network is able to compensate for the estimation error of the Kalman filter. In the project, Normalized Root Mean Square Error (NRMSE), which measures the difference between the filter’s estimates and actual ground truth data, is used as the evaluation criteria for fusion filter performance. After applying RBFNN to the fusion filter system, the NRMSE of the CMKF is reduced by more than 30%. and the NRMSE of the EKF is improved by more than 20%. The promising results proves that a fusion filter combining neural network and conventional Kalman filter can achieve a better performance than the stand-alone conventional Kalman filter. The proposed neural network is a universal tool to compensate for the estimate error of different Kalman filter types. Since the camera was not applied in the test because of hardware failure, some features of sensor fusion could not be verified. For further improvement, plenty of training sets in more complex scenario should be collected for network training to make the fusion filter reliable on the real road. The association algorithm can be updated to achieve multiple object tracking.
A system for indoor positioning using ultra-wideband technology
(2017) Dädeby, Sebastian; Hesselgren, Joakim; Chalmers tekniska högskola / Institutionen för data- och informationsteknik (Chalmers); Chalmers University of Technology / Department of Computer Science and Engineering (Chalmers)
The global positioning system is used in a wide array of applications. The ability to get an accurate location of a person or object has led to a number of so-called location-based services, mainly in logistics but also in more consumer applications such as localized weather information etc. This works well where a clear view of the sky will enable the GPS system to pinpoint your location with sufficient accuracy. However, in an indoor environment the signals will be badly disrupted by the material between the user and the satellites, making it significantly harder to use the system to determine your location. Here, a localized system based on a different technology is needed to allow all of the incredibly useful applications based on the user position to continue functioning as intended. In this thesis multiple possible techniques for usage in indoor positioning are presented and what their main advantages and disadvantages are. A technology was then chosen to be implemented and evaluated, which was ultra-wideband technique because of its accuracy and robustness. This technique uses radio frequencies with large bandwidth to send a high amount of energy in a short pulse, making it robust to obstacles as well as enabling the time of the received signal to be accurately calculated. The end product is a working indoor positioning system using ultra-wideband technology with a high accuracy in line of sight, and graceful degradation in non-line of sight and mixed conditions. The latency is low enough to be able to use as a real-time location system, providing that the problems with the information transfer to the server over Ethernet are fixed. The system has the possibility of tracking multiple tags, and has an accuracy of 15 to 30 centimeters depending on the conditions. This coupled with the range of upwards of 20 meters means that the system is viable for a wealth of applications, and ultra-wideband is a strong contender for the large amount of systems targeted at indoor positioning applications.
A Universal-Verification-Methodology- Based Verification Strategy for High-Level Synthesis Design
(2022) Shen, Haonan; Zhong, Chi; Chalmers tekniska högskola / Institutionen för data och informationsteknik; Peterson, Lena; Larsson-Edefors, Per
High-level synthesis (HLS) enables automatic translation from high-level language code to register transfer level (RTL) code, which could be a potential method to improve the development efficiency for hardware design. However, a different verification flow should be introduced to guarantee the HLS design fulfills design specifications. The purpose of this thesis is to explore and develop a new universal-verification-methodology-based (UVM-based) verification workflow particularly for HLS design. A universal strategy is developed in two different vendors’ tools, Cadence Incisive™/Xcelium™ and Siemens Mentor Graphics QuestaSim ™/Visualizer™, including automatic scripts and highly-reusable code to verify the HLS C++ design and the HLS RTL design generated by Siemens Mentor Catapult™. The design under test is a complex 5G communication block design from Ericsson. We first investigated the existing Cadence-based UVM verification environment, and updated the current flow into an HLS-specialized flow. Then, we explored how the verification strategy is realized with Cadence tools including Incisive/Xcelium. After that, we developed an entire flow in Siemens Mentor Graphics environment, by migrating the existing UVM verification environment architecture with Siemens Mentor Graphics supported libraries and developed the automation process for compilation, optimization and simulation in Siemens Mentor QuestaSim/Visualizer. Furthermore, to test the feasibility of the Siemens Mentor Graphics flow we designed, the flow is applied to collect results of functional coverage and code coverage of an Ericsson’s IP block. In the process of reaching coverage closure, the intermediate results indicate the demands of developing a series of additional direct tests, and suggest potential changes in the test plan for regression test. Finally, based on results in practicing the HLS verification flow in Cadence and Siemens Mentor Graphics environment, summarized suggestions are given to Ericsson for further improvements in the HLS verification flow.
A VHDL Architecture for Auto Encrypting SD Cards
(2016) Davidsson, Alexander; Rasmusson, Torbjörn; Chalmers tekniska högskola / Institutionen för data- och informationsteknik (Chalmers); Chalmers University of Technology / Department of Computer Science and Engineering (Chalmers)
This thesis details the design of an encrypted SD-card adapter for journalists to be used in destabilized areas. The SD-card adapter should be designed to protect the journalist's photographs while allowing previewing of the photograph until the SD-card is powered down. The SD-card adapter is designed to appear as a generic SD-card adapter with the exception that it encrypts the data and hides any changes in the le system. The design is based around a FPGA with use of a publicly available IP-core for encryption. The SD-card adapter uses both symmetrical and asymmetrical encryption for protection of individual les. A soft-core is used for generating encryption keys, asymmetrical encryption and general management. Through use of software based emulation, the concept was proven feasible.
A Vibration-Powered Wireless Sensor Device for Machine Conditioning
(2022) ALMBRATT, ERIK; BYADARAHALLI MADHUSUDHAN; Chalmers tekniska högskola / Institutionen för data och informationsteknik; Chalmers University of Technology / Department of Computer Science and Engineering; Larsson-Edefors, Per; Petersson, Lena
Preventive maintenance is commonly accepted as an economical solution to prevent production stops. Machine conditioning may offer data, allowing a reduced frequency of maintenance. However, these machine conditioning sensors have to be maintained themselves, reducing users’ confidence in the data. It may also make machine conditioning monitoring economically infeasible in some applications. Vibration-based energy harvesting may provide a reliable and, most importantly, low maintenance energy source for such machine conditioning sensors. In this project we designed and evaluated the implementation of a vibration-logging wireless sensor device, transmitting over Bluetooth Low Energy 5, and powered by a commercially available electrodynamic vibration generator. The results show that it is reasonable to expect a usable power output of around 0.1 to 6mW, greatly depending on the vibration source. This amount of power enables microcontroller-based designs to operate indefinitely. However, the technology is limited by the low bandwidth of contemporary generators, making vibration-based energy harvesting difficult to implement. While vibration-based energy harvesting shows promise, it requires thorough investigations to be able to conclude whether an application is suitable for the technology.
Accelerating a Machine Learning Algorithm on a Graphics Processing Unit
(2021) KOTRAPPA, PRASANNA; LOGANATHAN, PRADEEP; Chalmers tekniska högskola / Institutionen för data och informationsteknik; Larsson-Edefors, Per; Stenström, Per
Life long learning from zero(LL0) is a lifelong learning algorithm that has a dynamic neural network architecture. Many machine learning tools perform poorly on dynamic structures due to the overhead of growing computational maps with expanding networks. This thesis explores the possibility of delivering higher performance for the LL0 algorithm compared to the existing PyTorch implementation by developing a custom solution. This developed solution has a strongly coupled mapping of the LL0 algorithm with the GPU to achieve hardware acceleration. A set of benchmarks are defined to compare the performance of the between implementations. Furthermore, the thesis develops a methodology to investigate potential bottlenecks and parallelism with the implementation mapped to a GPU. The thesis achieves a significant speedup of ×19.48 on the number of feedforward per unit of time, compared with the similar PyTorch implementation, on an MNIST dataset.
Active feedback control of photonic molecule microcombs
(2022) Lööf, Anton; Chalmers tekniska högskola / Institutionen för data och informationsteknik; Chalmers University of Technology / Department of Computer Science and Engineering; Larsson-Edefors, Per; Torres, Victor
Frequency combs generate coherent and evenly spaced spectral lines. This enables applications within optical communication, for wavelength division multiplexing; metrology, for measuring time and frequency; spectroscopy, for probing a sample at multiple frequencies at the same time, and more. One novel implementation of these devices consists of two coupled resonators in a planar integrated Si3N4 platform. The device, called a photonic molecule, generates a coherent frequency comb by four wave mixing from a single input laser. A frequency comb generated by this device has been actively stabilized by thermal control of the pump to resonator detuning. The feedback system measures the generated comb power and changes the temperature of the resonators, via integrated heaters, to thermo-optically alter the location of the longitudinal modes of the coupled resonators. This changes the detuning such that the converted power remains constant. The control system is evaluated by measuring the stability and phase noise of the repetition rate of the comb. Long term stability is found to increase five-fold with the controller enabled and phase noise is improved by 5 dB for offset frequencies within the integrating bandwidth of the controller compared to a free-running comb in the same state. These results enable the use of photonic molecules for spectroscopy by increasing the stability of the comb as well as for optical communication by reducing phase noise. The results also make the photonic molecule easier to work with as it becomes less sensitive to environmental effects.
Adaptive core assignment for Adapteva Epiphany
(2015) Alveflo, Erik; Chalmers tekniska högskola / Institutionen för data- och informationsteknik (Chalmers); Chalmers University of Technology / Department of Computer Science and Engineering (Chalmers)
The number of cores in many-core processors is ever increasing, and so is the number of defects due to manufacturing variations and wear-out mechanisms. Sacri cing cores for increased longevity and manufacturing yield is cheap when thousands of cores are available. We propose two systems for tolerating faulty cores through software recon guration. The systems are based on remapping the user application when faults occur. Tasks are moved from faulty cores to reserved spare cores. Both systems were developed using a prototype based approach. One is inspired by the Epiphany Software Development Kit while the other utilizes simulated annealing to optimize distances between communicating tasks. Simulated annealing can automatically map applications while adhering to design constraints, but it can take 40 minutes to map an application with 4000 cores using the Parallella board's ARM processor.
Advanced Synthesis ECOs with Gate Array Fillers
(2014) Chirayu, Shah; Chalmers tekniska högskola / Institutionen för data- och informationsteknik (Chalmers); Chalmers University of Technology / Department of Computer Science and Engineering (Chalmers)
Engineering Change Orders (ECOs) are commonly used in the Application Speci c Integrated Circuits (ASIC) industry to either x design bugs or to add new features to the design after rst tape out. Due to rapid increase in the design complexity the metalmask ECOs have become inevitable. Generally, redundant standard cells, known as spare cells, are used to realize such type of ECOs. However, these cells su er from a major drawback of having prede ned functionality and location [1]. As a result, their use becomes limited. To overcome this in exibility, gate array type spare cells are used. As the gate array spare cell is con gurable, it opens up new possibilities of doing big ECOs. On the other hand, most ECO algorithms o ered by the commercial tools are not smart enough to handle such type of ECOs. In order to overcome this limitation, designers prefer using conventional ASIC ow rather than realizing such big changes as an ECO. In this thesis, a methodology to implement large scale ECOs is presented. This methodology aims to overcome the existing limitations of using the ECO algorithms by incorporating conventional ASIC ow algorithms to perform an ECO. The methodology has been implemented using gate array type cells. Simulation results show that for a medium sized design (12k gates) the implementation consumed 60% more dynamic power and occupied 75% more area as compared to the using regular standard cells. However, if a proper gate array library containing all the required cells is used for mapping, this number would be reduced to 30% and 35% respectively. On the other hand, due to advantages like faster time to market and small manufacturing costs [2] the area and power overhead incurred get compensated.
An Embedded Real-Time Traffic Simulation Environment on Vehicle-In-Loop Framework for Autonomous Driving
(2021) CHANDRASHEKAR, VARSHA; WANG, XINYUAN; Chalmers tekniska högskola / Institutionen för data och informationsteknik; Larsson-Edefors, Per; Johansson, Roger
Autonomous driving(AD) and Advanced Driver Assistance (ADAS) functions are rapidly evolving. Extensive testing of these systems is necessary at every stage of development. To ensure high performance and safety of ADAS and AD, the development of test technology has to happen at least at the same pace to support development. In order to cater to a more realistic testing, Vehicle-in-loop (VIL) methodology integrates a real vehicle into a virtual traffic environment to validate the vehicle’s behaviour. This is both safe and resource efficient. Since it involves both physical/real actors and virtual actors from the simulator, for a timely execution of a test scenario we need a closed loop simulation, with each actor on the test track and simulator being aware of one-another. Closed loop simulation requires updating of trajectories dynamically to each actor based on their dynamic positions to be able to execute a defined traffic scenario. There needs to be synchronized flow of information to and from the actors in real time. In this thesis, we worked on the development of a server on an embedded real time hardware platform. The server is a centralized controller steering test targets along given real time updated trajectories. This server is capable of controlling all the test targets by communicating with them via User Datagram Protocol (UDP) over Wi-fi, in a synchronized manner to provide for a closed loop simulation in real time as a part of VIL. We also studied an existing traffic simulator developed in Simulink and analyzed the different sources of latencies in the system. These latencies lead to scenarios failing to execute in real time due to synchronization errors. As an approach to solving these timing issues, we deployed this simulator onto the same real time platform as the server. The test results showed that the server could steer a Radio Controlled (RC) car in synchronization with the virtual actor generated by the simulator both in open loop and closed loop. Synchronization was achieved by making all the actors refer to a global time stamp and by reducing latencies in the simulator to meet all real time execution constraints.
Architecture and Performance Evaluation of the Space Communication Protocol Proximity-1
(2015) Eliasson, Malin; Hassel, Johan; Chalmers tekniska högskola / Institutionen för data- och informationsteknik (Chalmers); Chalmers University of Technology / Department of Computer Science and Engineering (Chalmers)
The amount of data generated during missions to other planets is ever-increasing. To accommodate the requirements on communication equipment, relay communication such as lander-satellite-earth links are used. For short-range communication between a lander and a satellite, protocols such as Proximity-1 are used. This report describes the implementation, testing and evaluation of the Data link layer of the Proximity-1 space communication protocol. The implementation, called Proximity-1 module, can establish a communication session with a remote Proximity-1 transceiver, transfer data, and reconfigure the radio link if needed. The Proximity-1 module is entirely implemented in hardware in order to off-load work from the On-Board Computer (OBC) of the system in which the module is used. The Proximity-1 module is designed to be as exible as possible in order to ease the task of incorporating it into a host system. The internal design of the Proximity-1 module is divided into blocks which correspond to the sublayers defined in the Proximity-1 standard. Each block is connected using streaming handshake interface. The well-defined block functionality and handshaking interfaces means that blocks implementing additional functionality can easily be added into the design for future expansions. In order to ensure an efficient design, the module is designed to provide an evenly distributed workload throughout the implementation. In addition, a performance enhancing acknowledgment strategy which is not part of the Proximity-1 standard is proposed and implemented. The configuration can be used to reduce the number of acknowledgment messages sent in a communication session and hence increase the effective data throughput.
ASIC System Design Considerations for Under-glass Fingerprint Sensors An investigation into system performance using capacitive technology
(2018) ARVIDSSON, JOHANNES; Söderström Olsson, Rasmus; Chalmers tekniska högskola / Institutionen för data- och informationsteknik (Chalmers); Chalmers University of Technology / Department of Computer Science and Engineering (Chalmers)
Placing a fingerprint sensor under thick glass puts heavy performance requirements on the mixed signal path in the ASIC that constitutes the sensor. This thesis will explore and explain different effects that can be observed when the distance between a finger and a capacitive sensor is increased. We will motivate why these effects are detrimental to performance and try to combat them with proposed system-level design changes. Fast-capture of fingerprint images have been used to characterize contrast over time; the time behavior of contrast could not be used to circumvent detrimental effects of using thick glass. Instead, focus has been placed on reducing noise using extensive multisampling, using a dynamic sample count based on finger movement, with positive results. A reduction in pixel noise power of approximately 50% compared to a currently used sensor design has been achieved within the same sampling time frame.

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